Low-damage plasma processing is the constraint below 5 nm. The four damage mechanisms, what ALE, pulsed and cryogenic etch fix, and what each costs.
Plasma made modern semiconductor manufacturing possible. It is also, at current dimensions, the process step most likely to break the device it is building. Below the 5 nm node, the limiting question in etch is no longer how fast material can be removed, but how little collateral damage the removal leaves behind.
Low-damage plasma processing is a set of techniques for removing or depositing material with a plasma while minimising the unintended modification of the surrounding material, caused by energetic ion bombardment, vacuum ultraviolet photons, surface charging and chemical intermixing. The objective is not simply a slower etch. It is decoupling the *chemistry* of the reaction from the *energy* delivered to the surface, so the reaction proceeds while the substrate underneath is left electrically and structurally intact.
At 90 nm, a few nanometres of damaged silicon at the bottom of a trench was a rounding error. In a gate-all-around transistor with a 5 nm nanosheet channel, the same few nanometres is the device.
Plasma-induced damage is not one phenomenon. It has four largely independent origins, and a fix for one does nothing for the others.
Ions accelerated across the sheath arrive with energies of tens to hundreds of electronvolts. They break bonds, displace lattice atoms and drive species several nanometres below the nominal etch front. In silicon this shows up as an amorphised subsurface layer; in III-V and 2D materials it can be catastrophic. Ion energy is the primary knob, and the primary conflict, because the same energy that damages the surface is what makes the etch anisotropic.
Plasmas radiate strongly in the vacuum ultraviolet. Those photons penetrate far deeper than ions, and they are not stopped by a sacrificial layer. In porous low-κ SiOCH dielectrics, VUV exposure depletes carbon from the film, raising the dielectric constant and destroying the very property the material was chosen for. This has been documented extensively for Ar/O₂ plasma exposure of low-κ films [1][4].
Electrons and ions do not arrive at a patterned surface with equal spatial distribution. Charge accumulates on insulating features and on conductive structures connected to large exposed areas. The resulting potential can drive current through a thin gate oxide and degrade or destroy it. This is the classic antenna effect, and it scales badly: thinner gate dielectrics tolerate less charge [2].
Fluorocarbon and chlorine chemistries leave residues, form sidewall polymer, and drive intermixing at the interface. The visible symptoms are line edge roughness, sidewall tapering, notching at the base of a feature, and selectivity loss against the mask or the underlying stop layer.
Three structural changes converged.
Vertical architecture. FinFET and gate-all-around structures present three-dimensional surfaces to a fundamentally directional process. Etching a fin sidewall uniformly from top to bottom is a different problem from etching a flat film.
Aspect ratio. High-aspect-ratio contact and 3D NAND channel etches run to ratios beyond 60:1. Ions must traverse the full depth without deflecting, while neutrals must reach the bottom and reaction products must get out.
Material diversity. The stack no longer contains only silicon, oxide and nitride. It contains porous low-κ dielectrics, high-κ metal gates, SiGe, III-V channels and 2D materials, each with a different and often much lower damage threshold.
| Technique | Mechanism | What it fixes | What it costs |
|---|---|---|---|
| Atomic layer etching (ALE) | Separates surface modification and removal into self-limiting steps | Ion energy per cycle drops below the damage threshold; near-perfect uniformity | Throughput. Removal is per-cycle, not continuous |
| Pulsed plasma | Modulates source or bias power in the kHz range | Lowers time-averaged ion energy, reduces charging by allowing negative-ion neutralisation | Process window complexity, added tuning parameters |
| Cryogenic etching | Cools the substrate to sub-zero temperatures | Passivates sidewalls without polymer deposition, improves selectivity and profile | Wafer temperature control hardware, condensation management |
| Remote / downstream plasma | Generates plasma away from the wafer, delivers only neutral radicals | Removes ion bombardment and most VUV exposure entirely | Loss of anisotropy. Isotropic only |
| Low-Te sources | Reduces electron temperature, narrowing the ion energy distribution | Softer bombardment, less dissociation of feed gas | Lower plasma density, slower rates |
Atomic layer etching is the technique the industry converged on for the cases where damage is the binding constraint. Its logic is deliberately close to atomic layer deposition: a self-limiting modification step, a purge, and a removal step whose energy is set below the threshold at which unmodified material would be sputtered. Kanarik and colleagues set out the industrial framing and the practical limits [3].
The cost is arithmetic. If a cycle removes one monolayer and the target is 5 nm, the process runs tens of cycles. ALE is therefore applied surgically, at the specific steps where an isotropic recess, a channel release, or a high-κ interface makes conventional continuous etch unacceptable, rather than across the whole flow.
Every low-damage technique trades throughput, anisotropy or process complexity for damage reduction. There is no configuration that gives all three.
Process integration is the discipline of choosing which of these to accept at each step in a flow of several hundred masks. The underlying plasma-surface interaction physics that sets those limits is summarised by Oehrlein and Hamaguchi [5].
Selectivity by design rather than by tuning. Area-selective deposition and atomic layer processes that exploit chemical contrast between materials, instead of relying on ion directionality to protect what should not be etched.
Sensor-driven endpoint control. Optical emission spectroscopy and impedance signatures feeding real-time models, so a cycle terminates when the surface says it is done, not when a timer expires.
Damage-aware metrology. Measuring subsurface amorphisation and carbon depletion inline, not on a monitor wafer three days later.
Thermal budget as a first-class variable. Cryogenic and elevated-temperature etch both work by changing surface reaction kinetics rather than ion energy. Precise wafer temperature control is becoming as important as RF control.
A note on scope, because the connection is not obvious and pretending otherwise would be dishonest.
YPlasma does not build etch tools. Our work is in dielectric barrier discharge at atmospheric pressure, generating airflow for thermal management, a very different regime from the millitorr, high-density plasmas used in fabrication. What the two share is the underlying physics of non-thermal, low-temperature plasma: sheath behaviour, energy coupling, dielectric ageing under continuous electrical stress, and the discipline of controlling where energy is deposited.
There is also a direct practical overlap. Process chambers, RF generators, control electronics and metrology systems all sit in an environment where thermal stability determines process stability, and where particulate from conventional fan cooling is unwelcome. Solid-state, no-moving-parts airflow is a relevant answer to that problem.
What is low-damage plasma processing? A set of plasma etch and deposition techniques designed to minimise unintended modification of the substrate, principally from ion bombardment, VUV photons, surface charging and chemical intermixing.
What causes plasma-induced damage in semiconductor manufacturing? Four independent mechanisms: energetic ion bombardment, vacuum ultraviolet photon exposure, charge accumulation on patterned surfaces, and chemical residue or intermixing at interfaces.
Does atomic layer etching eliminate plasma damage? It reduces it substantially by keeping per-cycle ion energy below the damage threshold and making each step self-limiting. It does not eliminate VUV exposure, and it costs throughput.
Why does plasma damage matter more at advanced nodes? Because the damaged layer has not shrunk while the device has. A few nanometres of subsurface amorphisation is negligible in a 90 nm transistor and is the entire channel in a 5 nm nanosheet.
Is cryogenic etching a low-damage technique? Yes, indirectly. It passivates sidewalls through temperature-dependent surface chemistry rather than through polymer deposition, which improves profile and selectivity without raising ion energy.
Related reading: plasma-based processes in chip manufacturing, thermal management for semiconductor equipment, and plasma actuators.